Search the 13 jobs at InnoPhase

As a Staff Engineer, Digital Design, you will be working with a team of design engineers to develop novel 5G ORAN SoC products for connectivity and wireless communications.

As a Principal Engineer/Manager, ASIC Physical Design at InnoPhase, you will lead the development of novel ASIC solutions for cellular infrastructure radio. Responsibilities include chip integration, block-level implementation, clock tree planning, resolving design issues, and managing quality deliverables.

Key contributor in ORAN SoC product development, collaborating with design team for product requirements and micro-architecture study. Implement and verify ORAN SoC functional blocks for high-performance applications. Provide technical advice and mentor junior engineers. Coordinate projects and improve design methodologies.

Tech Lead, FPGA Design & Verification role at InnoPhase, a communications semiconductor company pioneering a 5G platform. Responsibilities include developing FPGA designs, verifying specifications, debugging, synthesis, and contributing to system design methodologies. Requires 10+ years of experience with FPGA architecture, Xilinx tools, embedded systems, and wireless protocols.

Individual contributor to develop Embedded Linux-based SW solutions for O-RAN Cellular base station radios. Design and implement Front Haul Gateway on FPGA and Network Processor-based SoCs. Assist with the definition, development & verification of FW/SW products. Establish unit level design, implementation & test strategies. Support integration & test and debug software for timely closure. Work with the Applications team and customers to provide the necessary support.

Design and develop firmware/software for a 5G SoC, participate in architecture & code reviews, produce documentation, provide technical leadership, mentorship, and resolve technical issues.

As a Technical Lead in Design Verification at InnoPhase, you will lead ORAN SoC product design verification team, collaborate with FW & design team, develop testbench environments, and provide technical guidance to young engineers. This is an opportunity for engineers with 10+ years of experience to grow technically and in leadership roles in the cellular product market space.

Responsible for developing novel cellular infrastructure radio FPGA and ASIC solutions, including embedded Linux-based software. Collaborate with software engineers, perform synthesis and debugging, and contribute to specifications and architectures.

Design and develop firmware/software for a 5G SoC, collaborate with cross-functional teams, participate in code reviews, and provide technical leadership and mentorship. Strong coding skills in C, C++, Python, and experience with ARM embedded SoC development and RTOS principles are required.

Individual contributor to develop Embedded Linux-based SW solutions for O-RAN Cellular base station radios. Design and implement Front Haul Gateway on FPGA and Network Processor-based SoCs. Assist with the definition, development & verification of FW/SW products.

Senior Engineer responsible for building and improving CI/CD tools, processes, and infrastructure. Collaborate with Development and QA teams, own production incidents, and propose solutions for continuous delivery. Must have 9+ years of IT experience and strong skills in SVN, GIT, UDeploy, Jira, Linux, Windows, and scripting languages like Bash, Ruby, Perl, Python.

The Staff Engineer, Layout Design will work on developing novel SoC products for connectivity and communications, focusing on IC layout of analog/mixed-signal, RF, and digital designs in CMOS technologies. Responsibilities include floor planning, layout of block and top-level cells, and improving layout development flows. The ideal candidate is methodical, diligent, and disciplined.

Collaborate with a team of design engineers to develop novel SoC products for connectivity and communications. Contribute to product definition and detailed device specifications. Support other discipline teams for successful mass production.